Welcome to the BeaEngine Sweet Home - x86 x86-64 disassembler library - (IA-32 & Intel64)

Documentations

you can find here some ressources in relation with disassembly. You can find official documentations and more undocumented ones.

official intel documentation

These manuals describe the architecture and programming environment of the Intel« 64 and IA-32 processors.

Volume 1 , chapter 3 - Basic Execution Environment : Registers , OperandSize, AddressSize and all the operand addressing modes.

Volume 1 , chapter 4 - Data Types : All about datas formats.

Volume 1 , chapter 5 - Instruction Set Summary : Description of all intel instructions classified by categories.

Volume 1 , Appendice A - EFLAGS Cross-Reference : Synthesis on influence of instructions on eflags register

Volume 2A, chapter 2 - Instruction Format : Complete description of the format instruction, MOD, RM, SIB, prefixes and addressing modes.

Volume 2A, chapter 3 - Instruction Set Reference A-M : List of instructions in alphabetic order.

Volume 2B, chapter 4 - Instruction Set Reference N-Z : List of instructions in alphabetic order

Volume 2B, Appendice A Opcode Map : Tables containing opcodes. BeaEngine is using these tables.

official AMD documentation

AMD documentation is mandatory because we must admit that it is usually more understandable than the intel one.

Sandpile

This is the famous Christian Ludloff's web site with the most complete list of opcodes (even undocumented) for intel and AMD.

X86 Opcode and Instruction reference

This is the MazeGen's web site where you can find a complete list of intel and AMD instructions presented under some useful formats (xml...).

Documentation about encoding

This document (in french), describes in a precise way the manner of how to encode instructions on AMD and intel architecture x86 and x86-64.The first volume is about basic encoding whereas the second is about prefixes and diffrences between architectures AMD64 and intel64.

Author : Neitsa

Valid XHTML 1.0 Strict

Valid CSS!